The filter switching type phase shifter is usually made up by a high-pass filter (HPF) for producing the phase lead of the signal phase, a lowpass filter (LPF) for producing the phase lag of the signal phase and single pole double throw switches (SPDT switches) for switching between the high-pass and low-pass filters. The quantity of phase shift is created by the phase difference produced on switching between these two filters.
The configuration of this filter switching type phase shifter will now be explained. FIG. 4 depicts a circuit diagram of a state-of-the-art filter switching type phase shifter. A high-pass filter (HPF) 102 is made up by two capacitors C101, C102, connected in series with a signal line, and an inductor L101, connected from a junction of the two capacitors C101, C102 to the ground. A low-pass filter (LPF) 103 is made up by two inductors L102, L103, connected in series with a signal line, and a capacitor C103, connected from the junction of the two inductors L102, L103 to the ground. The high-pass filter 102 and the low-pass filter 103 are connected via a single pole double throw switch (SPDTSW) 101a to an input terminal IN, while being connected via a single pole double throw switch (SPDTSW) 101b to an output terminal OUT.
The operation of the phase shifter, constructed as described above, will now be explained. If, when a signal from the input terminal IN to the output terminal OUT is passed through the high-pass filter 102, a bias, not shown, operating for turning an FET (field effect transistor) Q101 on, is applied to the gates of FETs (field effect transistors) Q101 and Q103, the source-drain resistance is lowered to establish a practically short-circuited state, and hence the current is allowed to pass through the high-pass filter 102. At this time, a bias, not shown, turning FETs Q102 and Q104 off, is applied across the gates of FETs Q102 and Q104, so that the resistance across the sources and the drains of the FETs Q102 and Q104 is increased, such that, from the signal line, the FETs Q102 and Q104 appear to be open-circuited, there being no current flowing through these FETs.
On the other hand, a bias voltage, not shown, which turns off the FET, is applied to the gates of the FET Q105 and the FET Q107, in order to inhibit the current flowing to the low-pass filter, thereby increasing the source-drain resistance of the FET Q105 and FET Q107. Moreover, a bias voltage, not shown, which turns on the FET, is applied to the gates of the FET Q106 and the FET Q108, thereby decreasing the source-drain resistance of the FET Q106 and FET Q108 to ground the weak current passed through the FETs Q105, Q107.
On the other hand, when the low-pass filter 103 is turned on, the signal is allowed to flow to the low-pass filter 103 by applying the bias which is the reverse of that described above to the gates of the FETs of the single pole double throw switches 101a, 101b. 
In this manner, the single pole double throw switches 101a, 101b are changed over so that signals will flow through the high-pass filter 102 or the low-pass filter 103. The input signal will lag by the inductors L102, L103, connected in series with the low-pass filter 103, when the signal is passed through the low-pass filter 103, while the input signal will lead by the capacitors C101, C102, connected in series with the high-pass filter 102. Hence, the phase difference of the input signal is produced by changing over the filter units by the single pole double throw switches 101a, 101b. It is noted that, for realizing a desired phase shift value, the values of the components in the respective filter units need to be changed to optimum values.
Meanwhile, with the high frequency band, such as the GHz band, the effect of parasitic components of the FETs of the single pole double throw switches are demonstrated, such that the input/output impedance of the phase shifter becomes different at the time of switching between the high-pass filter 102 and the low-pass filter 103. The result is that signal insertion loss difference or the impedance mismatch between the load impedance and the filter units is produced to cause variations in the phase shift value. In order to combat this problem, the technique of reducing the effect of parasitic components of the single pole double throw switch is disclosed in Patent Document 1.
The phase shifter, disclosed in Patent Document 1, includes a resistance matching circuit in the input and output sides of switching means. This resistance matching circuit is made up of a matching inductor, connected in series with a signal transmission channel for canceling out the reflection ascribable to capacitance, at the time of turning off of the field effect transistor, and a matching resistor connected in parallel with the signal transmission channel for canceling out the reflection ascribable to parasitic resistance at the time of turning on of the field effect transistor.
As a relevant technique, Patent Document 2 discloses subjecting the high frequency signal entered to an input/output terminal to impedance changing by a matching stub.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2002-76810A (FIG. 4)
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-11-330802 (FIG. 1)